Intel Plus Altera
Since the Intel-Altera deal reached the handshake phase earlier this month, there have been a lot of theories being forwarded and a lot of questions being raised. And there have been very few answers,...
View ArticleThe Future Of Moore’s Law
Semiconductor Engineering sat down to discuss the future of Moore’s Law with Jan Rabaey, Donald O. Pederson distinguished professor at University of California at Berkeley; Lucio Lanza, managing...
View ArticleExecutive Insight: Wally Rhines
Wally Rhines, chairman and CEO of Mentor Graphics, sat down with Semiconductor Engineering to talk about what’s changing across a wide swath of the industry, where the new opportunities will be, when...
View ArticleExecutive Insight: Aart de Geus
Aart de Geus, chairman and co-CEO of Synopsys, sat down with Semiconductor Engineering to talk about acquisitions, software and EDA. What follows are excerpts of that interview, which was conducted in...
View Article2.5D Creeps Into SoC Designs
A decade ago top chipmakers predicted that the next frontier for SoC architectures would be the z axis, adding a third dimension to improve throughput and performance, reduce congestion around...
View ArticleChallenges At Advanced Nodes
Semiconductor Engineering sat down to discuss finFETs, 22nm FD-SOI and how the how the market will segment over the next few years with Marie Semeria, CEO of Leti; Patrick Soheili, vice president of...
View ArticleInterconnect Challenges Grow
It’s becoming apparent that traditional chip scaling is slowing down. The 16nm/14nm logic node took longer than expected to unfold. And the 10nm node and beyond could suffer the same fate. So what’s...
View ArticleElectronics Butterfly Effect
Everyone has heard of the butterfly effect where a small change in a non-linear system can result in large difference in an outcome. For the past 40 years, the electronics industry has approximated a...
View ArticleRethinking Differentiation
Differentiation is becoming more difficult, more time-consuming, and in some cases much more expensive for chipmakers. The traditional metrics of faster performance, lower power and less area/cost,...
View ArticleChallenges At Advanced Nodes
Semiconductor Engineering sat down to discuss finFETs, 22nm FD-SOI and how the how the market will segment over the next few years with Marie Semeria, CEO of Leti; Patrick Soheili, vice president of...
View ArticleNew Options For Power
Chipmakers have been talking for years about the next big breakthrough in battery technology, low-power architectures and energy harvesting. So far, none of them has made their job any easier....
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We Must Teach Chips To Feel Pain
By Guido Groeseneken When I was a doctorate student in the 1980s there was lots of wild speculation about Moore’s Law: give it another 10 years and transistors will stop getting smaller, they were...
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SEMICON Taiwan’s Packaging Punch
SEMICON Taiwan packed a punch, setting several new records and new heights in 2015. This year marked the 20th anniversary of SEMICON in Taiwan and was the largest SEMICON in Taiwan ever, with a Nobel...
View ArticleRaise A Fence, Dig A Tunnel, Build A Bridge
There are three main options for chipmakers over the course of the next decade. Which option they choose depends upon their individual needs, talents, and how much and what kind of differentiation they...
View ArticleIs HW Or SW Running the Show?
In the past, hardware was designed and then passed over to the software team for them to add their contribution to the product. This worked when the amount of software content was small and the...
View ArticleIs The 2.5D Supply Chain Ready?
A handful of big semiconductor companies began taking the wraps off 2.5D and fan-out packaging plans in the past couple of weeks, setting the stage for the first major shift away from Moore’s Law in 50...
View ArticleSecurity In 2.5D
The long-anticipated move to 2.5D and fan-outs is raising some familiar questions about security. Will multiple chips combined in an advanced package be as secure as SoCs where everything is integrated...
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Tech Talk: 14nm And Stacked Die
Aashish Malhotra, marketing director for the ASIC Business Unit at GlobalFoundries, talks about 14nm process technology, the IP ecosystem, and why that technology node will be used as a platform for...
View ArticleOvercoming The Design Bottleneck
SoCs control most advanced electronics these days and functionality, quality, power and security are a combination of both hardware and software. All throughout the development of today’s complex...
View ArticlePlacing Bets On Future Technology
Marie Semeria, CEO of Leti, sat down with Semiconductor Engineering to talk about where the French research and technology organization is placing its future technology bets and what’s behind those...
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